1. Field of the Invention
The present invention relates to the recovery of clock timing information from data transmitted within digital systems. More specifically, this invention relates to phase-locked methods of clock recovery within digital systems such as local area networks (LANs).
While the present invention is described herein with reference to a particular embodiment, it is understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional embodiments within the scope thereof.
2. Description of the Related Art
The interest in local-area networks is steadily increasing. Local area networks facilitate economical data communication between computing systems clustered in a locality. One such network widely used in the art is known as a token ring LAN.
A token ring LAN is a circular network having a plurality of stations (nodes) interconnected in a ring topology. Access to the network is controlled by the possession of a signal "token". The token is a packet of signals that is passed from node to node. The node that has the token has control of the network with respect to the transmission of data to other nodes and the receipt of data from the same. When the node has completed a transmission, the token is released for acquisition by another node.
Errors in data transmission within the ring can generally be minimized by operating the ring in a synchronous mode. That is, in order to decode a baseband data waveform a clock signal giving the proper sampling time must be available. Pilot tones are sometimes transmitted along with the data waveform for this purpose. Alternatively, timing may be derived directly from the data waveform itself. One approach to such "self-timing" involves allowing the data to pass through a memoryless nonlinearity and then ring a tuned circuit with a resonant frequency close to the nominal data (bit) rate. Nonetheless, this approach is relatively imprecise in comparison with those which utilize phase-locked loops (PLL's).
Conventional PLL's generally include a phase/frequency detector (PFD) for generating an error signal in response to the phase difference between an input data stream and a recovered clock signal. A charge pump and associated filter network usually accompany the PFD in order to convert the logic states thereof into analog signals suitable for controlling a voltage controlled oscillator (VCO). The VCO, in turn, produces the recovered clock signal.
The efficacy of PLL's employed in LAN's with regard to the extraction of a clock frequency from a data waveform generally depends largely on the performance characteristics of the PFD, as well as on the transmission code selected. In this regard, the Manchester code is often favored within LAN's as allowing for relatively simple clock extraction since a rising or falling data transition occurs at every midbit interval irrespective of the specific data pattern. Despite the numerous possible realizations of the PFD, however, nearly all are disposed to produce an error signal only upon the occurrence of data transitions in a single direction. For example, "rising edge" phase detectors will perform a phase comparison and issue an error signal only with regard to data bits which include a rising transition. Accordingly, even in systems utilizing Manchester coding an error correction signal will not be produced by the PFD every clock period.
There exist at least two disadvantages resulting from the failure to generate an error signal during each clock period. First, the recovered clock signal may undergo an unacceptably large drift in phase during the interval between successive correction signals. Second, the loop gain of the PLL will fluctuate depending on the density of rising and falling transitions within the data waveform. It follows that a data pattern having a high density of, for instance, rising edge transitions will induce a rising edge phase detector to inject a relatively large number of correction signals into the PLL. The resulting increase in gain within the PLL is thus seen to be a function of the stimulus of the data pattern. Unfortunately, variations in loop gain due to data pattern differences may be magnified between chain-connected PLL's so as to introduce undesired effects such as timing jitter accumulation.
Accordingly, a need in the art exists for a PLL timing recovery scheme in which loop performance is substantially unaffected by the specific composition of the incident data waveform.